
for its clock-on-receive. Programming of the clocks should be done before enabling the
receiver, transmitter, BRG, or DPLL.
External/Status interrupt control
Miscellaneous control bits: baud rate generator, DPLL control,
auto echo
Lower byte of baud rate time constant WR13
Lower byte of baud rate time constant WR12
Clock mode and source control
Miscellaneous transmitter/receiver control bits, NRZI, NRZ,
FM coding, CRC reset
Master interrupt control and reset WR9
Transmit bufferWR8
Special HDLC Enhancement Register
Sync character (2nd byte) or SDLC Flag
Sync character (1st byte) or SDLC address field WR6
Transmitter initialization and control
Transmit/Receive miscellaneous parameters and codes, clock
rate, stop bits, parity
Receiver initialization and control WR3
Interrupt vectorWR2
Interrupt control, Wait/DMA request control
Command Register, Register Pointer, CRC initialization, and
resets for various modes
Table 4 --- SCC write register description
For complete information regarding the SCC registers please refer to Zilog's
Z85230 technical manual.
Quatech MPAC-100 User's Manual
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